The invention generally relates to the cube packaging of a stack of semiconductor device chips and more particularly, to such packaging using insulating and adhesive materials permitting faster device operation, greater package reliability and enhanced package compatibility with existing semiconductor device processing techniques.
As is well known, the so-called "cube" package is a number of passivated device chips glued together in a stacked configuration. Each chip may have an "off-the-shelf" design layout including surface contact metallization. To accommodate "cube" packaging, each such device chip additionally is provided with a metal transfer layer over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. Precise alignment of the chips, during the stacking and gluing assembly, allows for the bussing of all the common input-output lines on one or more faces of the resulting cube structure.
U.S. Pat. No. 4,525,921, issued on Jul. 2, 1985, to John C. Carson et al. for "High Density Electronic Processing Package Structure and Fabrication" discloses an early version of cube packaging involving the use of specially routed chip-edge contact metallization on each passivated chip face avoiding the need for a metal rerouting layer. Silicon dioxide is added to the backside of each chip to complete the electrical isolation of the chips from each other in the stack. The silicon dioxide-isolated chips are fixed to each other by means of a bonding epoxy.
The need for special chip-edge contact metallization routing on each chip is eliminated in later U.S. Pat. No. 5,104,820, issued Apr. 14, 1992, to Tiong C. Go et al. for "Method of Fabricating Electronic Circuitry Unit Containing Stacked IC Layers Having Lead Rerouting". A metal rerouting layer is provided to accommodate the stacking of standard off-the-shelf chips having conventional face mounted contact metallization. The latter patent contemplates the use of certain ordinary insulation films between the aforesaid two layers of metallization as well as on the backside of each chip. Rather than using exclusively oxide insulation between the chips as in the case of U.S. Pat. No. 4,525,921, SiON also is suggested in U.S. Pat. No. 5,104,820 for covering the upper (device side) surface of each chip to isolate the original chip contact metallization from the added rerouting metallization. Silicon nitride is cited to cover the backside of each chip rather than the silicon dioxide of U.S. Pat. No. 4,525,921. An epoxy adhesive is used to fix adjacent stacked chips to each other.
Referring to prior art FIG. 1a, an individual chip 1 is shown having contact metallization 2 which extends to the side surface 3 of the chip. It should be noted that chip 1 also is complete with semiconductor circuit devices and device interconnection metallurgy. Chip 1 may be designed to function as a memory chip, logic chip, or any memory and logic combination chip, for example. The metallization 2 may be designed as part of the original chip surface connections so that module interconnections could be made to pads on the edge 3. Alternatively, and as described in the aforementioned U.S. Pat. No. 5,104,820, the interconnection metallurgy may be designed as second level rerouting metal conductors (insulated from the original silicon and its aluminum or other metallization) which contact the original metallization and extend to pads on the chip edge 3. As previously noted, the latter case permits the use of "off-the-shelf" chips which were designed without regard to their later inclusion in cube packaging.
The individual chips 1 are provided with insulating layers under the rerouting metal as well as over the backsides of the chips and are then fixed together with an epoxy adhesive in the cube or stacked configuration of FIG. 1B. Those edge-mounted contact pads which can be connected together (such as power inputs) are ganged by means of busses as shown in FIG. 1C. FIG. 1D is a simplified top view of the resulting structure, showing the cube 1 disposed on an interposer 4, having metal lines 4A that are coupled to the cube bus wiring through conventional solder bump interconnection technology (not shown). The metal lines 4A extend to the periphery of interposer 4, where they are coupled to the interconnecting pins P of package 5 via wirebonds 5A. Note that in the prior art, silicon interposer 4 is necessary to match the thermal expansion coefficient of the silicon chips (that is, because it is made of silicon the interposer will have the same TCE as the chips in the cube). However, the present inventors have noted that while the use of a silicon interposer accounts for the TCE of the chips themselves, it does not address differential chip-to-chip TCE caused by the epoxy used to bond the chips to one another. The best solution would be to eliminate the silicon interposer completely.
Moreover, the foregoing references fail to optimize the electrical properties of the resulting cube. Specifically, the epoxy used to bond the chips to one another is conventionally a high dielectric constant material that is applied as the chips are bonded together. As such, the epoxy material does not optimize the characteristics of the resulting cube package with respect to the operating speed of the contained semiconductor devices, the reliability of the package and the compatibility of the package with respect to existing semiconductor device processing and packaging techniques.